Python based FPGA design-flow

Simple item page
dc.contributor.advisorInggs, Michaelen_ZA
dc.contributor.advisorWinberg, Simonen_ZA
dc.contributor.authorNew, Wesleyen_ZA
dc.date.accessioned2016-07-14T12:17:25Z
dc.date.available2016-07-14T12:17:25Z
dc.date.issued2016en_ZA
dc.description.abstractThis dissertation undertakes to establish the feasibility of using MyHDL as a basis on which to develop an FPGA-based DSP tool-ow to target CASPER hardware. MyHDL is an open-source package which enables Python to be used as a hardware definition and verification language. As Python is a high-level language, hardware designers can use it to model and simulate designs, without needing detailed knowledge of the underlying hardware. MyHDL has the ability to convert designs to Verilog or VHDL allowing it to integrate into the more traditional design-ow. The CASPER tool- ow exhibits limitations such as design environment instability and high licensing fees. These shortcomings are addressed by MyHDL. To enable CASPER to take advantage of its powerful features, MyHDL is incorporated into a next generation tool-ow which enables high-level designs to be fully simulated and implemented on the CASPER hardware architectures.en_ZA
dc.identifier.apacitationNew, W. (2016). <i>Python based FPGA design-flow</i>. (Thesis). University of Cape Town ,Faculty of Engineering & the Built Environment ,Department of Electrical Engineering. Retrieved from http://hdl.handle.net/11427/20339en_ZA
dc.identifier.chicagocitationNew, Wesley. <i>"Python based FPGA design-flow."</i> Thesis., University of Cape Town ,Faculty of Engineering & the Built Environment ,Department of Electrical Engineering, 2016. http://hdl.handle.net/11427/20339en_ZA
dc.identifier.citationNew, W. 2016. Python based FPGA design-flow. University of Cape Town.en_ZA
dc.identifier.ris TY - Thesis / Dissertation AU - New, Wesley AB - This dissertation undertakes to establish the feasibility of using MyHDL as a basis on which to develop an FPGA-based DSP tool-ow to target CASPER hardware. MyHDL is an open-source package which enables Python to be used as a hardware definition and verification language. As Python is a high-level language, hardware designers can use it to model and simulate designs, without needing detailed knowledge of the underlying hardware. MyHDL has the ability to convert designs to Verilog or VHDL allowing it to integrate into the more traditional design-ow. The CASPER tool- ow exhibits limitations such as design environment instability and high licensing fees. These shortcomings are addressed by MyHDL. To enable CASPER to take advantage of its powerful features, MyHDL is incorporated into a next generation tool-ow which enables high-level designs to be fully simulated and implemented on the CASPER hardware architectures. DA - 2016 DB - OpenUCT DP - University of Cape Town LK - https://open.uct.ac.za PB - University of Cape Town PY - 2016 T1 - Python based FPGA design-flow TI - Python based FPGA design-flow UR - http://hdl.handle.net/11427/20339 ER - en_ZA
dc.identifier.urihttp://hdl.handle.net/11427/20339
dc.identifier.vancouvercitationNew W. Python based FPGA design-flow. [Thesis]. University of Cape Town ,Faculty of Engineering & the Built Environment ,Department of Electrical Engineering, 2016 [cited yyyy month dd]. Available from: http://hdl.handle.net/11427/20339en_ZA
dc.language.isoengen_ZA
dc.publisher.departmentDepartment of Electrical Engineeringen_ZA
dc.publisher.facultyFaculty of Engineering and the Built Environment
dc.publisher.institutionUniversity of Cape Town
dc.subject.otherElectrical Engineeringen_ZA
dc.subject.otherSoftwareen_ZA
dc.subject.otherProgramming Languages - Pythonen_ZA
dc.titlePython based FPGA design-flowen_ZA
dc.typeMaster Thesis
dc.type.qualificationlevelMasters
dc.type.qualificationnameMSc (Eng)en_ZA
uct.type.filetypeText
uct.type.filetypeImage
uct.type.publicationResearchen_ZA
uct.type.resourceThesisen_ZA
Files
Original bundle
Now showing 1 - 1 of 1
Thumbnail Image
Name:
thesis_ebe_2016_new_wesley.pdf
Size:
2.09 MB
Format:
Adobe Portable Document Format
Description:
Download
Collections
Masters