An FPGA implementation of an investigative many-core processor, Fynbos : in support of a Fortran autoparallelising software pipeline

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dc.contributor.advisorInggs, Michaelen_ZA
dc.contributor.advisorCollins, Jen_ZA
dc.contributor.authorWyngaard, Janet Ruthen_ZA
dc.date.accessioned2015-07-02T08:28:20Z
dc.date.available2015-07-02T08:28:20Z
dc.date.issued2014en_ZA
dc.descriptionIncludes bibliographical references.en_ZA
dc.description.abstractIn light of the power, memory, ILP, and utilisation walls facing the computing industry, this work examines the hypothetical many-core approach to finding greater compute performance and efficiency. In order to achieve greater efficiency in an environment in which Moore’s law continues but TDP has been capped, a means of deriving performance from dark and dim silicon is needed. The many-core hypothesis is one approach to exploiting these available transistors efficiently. As understood in this work, it involves trading in hardware control complexity for hundreds to thousands of parallel simple processing elements, and operating at a clock speed sufficiently low as to allow the efficiency gains of near threshold voltage operation. Performance is there- fore dependant on exploiting a new degree of fine-grained parallelism such as is currently only found in GPGPUs, but in a manner that is not as restrictive in application domain range. While removing the complex control hardware of traditional CPUs provides space for more arithmetic hardware, a basic level of control is still required. For a number of reasons this work chooses to replace this control largely with static scheduling. This pushes the burden of control primarily to the software and specifically the compiler, rather not to the programmer or to an application specific means of control simplification. An existing legacy tool chain capable of autoparallelising sequential Fortran code to the degree of parallelism necessary for many-core exists. This work implements a many-core architecture to match it. Prototyping the design on an FPGA, it is possible to examine the real world performance of the compiler-architecture system to a greater degree than simulation only would allow. Comparing theoretical peak performance and real performance in a case study application, the system is found to be more efficient than any other reviewed, but to also significantly under perform relative to current competing architectures. This failing is apportioned to taking the need for simple hardware too far, and an inability to implement static scheduling mitigating tactics due to lack of support for such in the compiler.en_ZA
dc.identifier.apacitationWyngaard, J. R. (2014). <i>An FPGA implementation of an investigative many-core processor, Fynbos : in support of a Fortran autoparallelising software pipeline</i>. (Thesis). University of Cape Town ,Faculty of Engineering & the Built Environment ,Department of Electrical Engineering. Retrieved from http://hdl.handle.net/11427/13265en_ZA
dc.identifier.chicagocitationWyngaard, Janet Ruth. <i>"An FPGA implementation of an investigative many-core processor, Fynbos : in support of a Fortran autoparallelising software pipeline."</i> Thesis., University of Cape Town ,Faculty of Engineering & the Built Environment ,Department of Electrical Engineering, 2014. http://hdl.handle.net/11427/13265en_ZA
dc.identifier.citationWyngaard, J. 2014. An FPGA implementation of an investigative many-core processor, Fynbos : in support of a Fortran autoparallelising software pipeline. University of Cape Town.en_ZA
dc.identifier.ris TY - Thesis / Dissertation AU - Wyngaard, Janet Ruth AB - In light of the power, memory, ILP, and utilisation walls facing the computing industry, this work examines the hypothetical many-core approach to finding greater compute performance and efficiency. In order to achieve greater efficiency in an environment in which Moore’s law continues but TDP has been capped, a means of deriving performance from dark and dim silicon is needed. The many-core hypothesis is one approach to exploiting these available transistors efficiently. As understood in this work, it involves trading in hardware control complexity for hundreds to thousands of parallel simple processing elements, and operating at a clock speed sufficiently low as to allow the efficiency gains of near threshold voltage operation. Performance is there- fore dependant on exploiting a new degree of fine-grained parallelism such as is currently only found in GPGPUs, but in a manner that is not as restrictive in application domain range. While removing the complex control hardware of traditional CPUs provides space for more arithmetic hardware, a basic level of control is still required. For a number of reasons this work chooses to replace this control largely with static scheduling. This pushes the burden of control primarily to the software and specifically the compiler, rather not to the programmer or to an application specific means of control simplification. An existing legacy tool chain capable of autoparallelising sequential Fortran code to the degree of parallelism necessary for many-core exists. This work implements a many-core architecture to match it. Prototyping the design on an FPGA, it is possible to examine the real world performance of the compiler-architecture system to a greater degree than simulation only would allow. Comparing theoretical peak performance and real performance in a case study application, the system is found to be more efficient than any other reviewed, but to also significantly under perform relative to current competing architectures. This failing is apportioned to taking the need for simple hardware too far, and an inability to implement static scheduling mitigating tactics due to lack of support for such in the compiler. DA - 2014 DB - OpenUCT DP - University of Cape Town LK - https://open.uct.ac.za PB - University of Cape Town PY - 2014 T1 - An FPGA implementation of an investigative many-core processor, Fynbos : in support of a Fortran autoparallelising software pipeline TI - An FPGA implementation of an investigative many-core processor, Fynbos : in support of a Fortran autoparallelising software pipeline UR - http://hdl.handle.net/11427/13265 ER - en_ZA
dc.identifier.urihttp://hdl.handle.net/11427/13265
dc.identifier.vancouvercitationWyngaard JR. An FPGA implementation of an investigative many-core processor, Fynbos : in support of a Fortran autoparallelising software pipeline. [Thesis]. University of Cape Town ,Faculty of Engineering & the Built Environment ,Department of Electrical Engineering, 2014 [cited yyyy month dd]. Available from: http://hdl.handle.net/11427/13265en_ZA
dc.language.isoengen_ZA
dc.publisher.departmentDepartment of Electrical Engineeringen_ZA
dc.publisher.facultyFaculty of Engineering and the Built Environment
dc.publisher.institutionUniversity of Cape Town
dc.subject.otherElectrical Engineeringen_ZA
dc.titleAn FPGA implementation of an investigative many-core processor, Fynbos : in support of a Fortran autoparallelising software pipelineen_ZA
dc.typeDoctoral Thesis
dc.type.qualificationlevelDoctoral
dc.type.qualificationnamePhDen_ZA
uct.type.filetypeText
uct.type.filetypeImage
uct.type.publicationResearchen_ZA
uct.type.resourceThesisen_ZA
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