Firmware and gateway for the ACE1 reconfigurable accelerator card

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dc.contributor.authorThorne, Nicholas Jamesen_ZA
dc.date.accessioned2015-01-02T08:53:53Z
dc.date.available2015-01-02T08:53:53Z
dc.date.issued2011en_ZA
dc.description.abstractThis thesis describes the continued work on the in-house designed FPGA based co-processor daughtercard referred to as ACE1. The aim: to create an ecosystem incorporating firmware, bootstrapping code, drivers and a development environment to create a seamless environment. Challenges in setting up and debugging the interface that connects the coprocessor daughtercard to the host server include: problems with the power network, the edge connectors and timing problems with the primary protocol which prevented host-based communications. The options include allowing the daughtercard to function in a stand-alone fashion and we present a gateware solution that allows users to select from a number of alternatives for each of the layers in the Open Systems Interconnect networking model.en_ZA
dc.identifier.apacitationThorne, N. J. (2011). <i>Firmware and gateway for the ACE1 reconfigurable accelerator card</i>. (Thesis). University of Cape Town ,Faculty of Engineering & the Built Environment ,Department of Electrical Engineering. Retrieved from http://hdl.handle.net/11427/10926en_ZA
dc.identifier.chicagocitationThorne, Nicholas James. <i>"Firmware and gateway for the ACE1 reconfigurable accelerator card."</i> Thesis., University of Cape Town ,Faculty of Engineering & the Built Environment ,Department of Electrical Engineering, 2011. http://hdl.handle.net/11427/10926en_ZA
dc.identifier.citationThorne, N. 2011. Firmware and gateway for the ACE1 reconfigurable accelerator card. University of Cape Town.en_ZA
dc.identifier.ris TY - Thesis / Dissertation AU - Thorne, Nicholas James AB - This thesis describes the continued work on the in-house designed FPGA based co-processor daughtercard referred to as ACE1. The aim: to create an ecosystem incorporating firmware, bootstrapping code, drivers and a development environment to create a seamless environment. Challenges in setting up and debugging the interface that connects the coprocessor daughtercard to the host server include: problems with the power network, the edge connectors and timing problems with the primary protocol which prevented host-based communications. The options include allowing the daughtercard to function in a stand-alone fashion and we present a gateware solution that allows users to select from a number of alternatives for each of the layers in the Open Systems Interconnect networking model. DA - 2011 DB - OpenUCT DP - University of Cape Town LK - https://open.uct.ac.za PB - University of Cape Town PY - 2011 T1 - Firmware and gateway for the ACE1 reconfigurable accelerator card TI - Firmware and gateway for the ACE1 reconfigurable accelerator card UR - http://hdl.handle.net/11427/10926 ER - en_ZA
dc.identifier.urihttp://hdl.handle.net/11427/10926
dc.identifier.vancouvercitationThorne NJ. Firmware and gateway for the ACE1 reconfigurable accelerator card. [Thesis]. University of Cape Town ,Faculty of Engineering & the Built Environment ,Department of Electrical Engineering, 2011 [cited yyyy month dd]. Available from: http://hdl.handle.net/11427/10926en_ZA
dc.language.isoengen_ZA
dc.publisher.departmentDepartment of Electrical Engineeringen_ZA
dc.publisher.facultyFaculty of Engineering and the Built Environment
dc.publisher.institutionUniversity of Cape Town
dc.subject.otherElectrical Engineeringen_ZA
dc.titleFirmware and gateway for the ACE1 reconfigurable accelerator carden_ZA
dc.typeMaster Thesis
dc.type.qualificationlevelMasters
dc.type.qualificationnameMScen_ZA
uct.type.filetypeText
uct.type.filetypeImage
uct.type.publicationResearchen_ZA
uct.type.resourceThesisen_ZA
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