Firmware and gateway for the ACE1 reconfigurable accelerator card

Master Thesis

2011

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http://hdl.handle.net/11427/10926
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thesis_ebe_2011_thorne_n.pdf (13.87 MB)
Authors
Thorne, Nicholas James
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University of Cape Town

Department
Department of Electrical Engineering
Faculty
Faculty of Engineering and the Built Environment
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Abstract
This thesis describes the continued work on the in-house designed FPGA based co-processor daughtercard referred to as ACE1. The aim: to create an ecosystem incorporating firmware, bootstrapping code, drivers and a development environment to create a seamless environment. Challenges in setting up and debugging the interface that connects the coprocessor daughtercard to the host server include: problems with the power network, the edge connectors and timing problems with the primary protocol which prevented host-based communications. The options include allowing the daughtercard to function in a stand-alone fashion and we present a gateware solution that allows users to select from a number of alternatives for each of the layers in the Open Systems Interconnect networking model.
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Electrical Engineering

Reference:

Thorne, N. 2011. Firmware and gateway for the ACE1 reconfigurable accelerator card. University of Cape Town.

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