Design of a scheduling mechanism for an ATM switch

Master Thesis

2003

Permanent link to this Item
http://hdl.handle.net/11427/5207
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thesis_ebe_2003_harvey_no.pdf (9.31 MB)
Authors
Harvey, Nicholas Oliver
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University of Cape Town

Department
Department of Electrical Engineering
Faculty
Faculty of Engineering and the Built Environment
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Abstract
In this dissenation, the candidate proposes the use of a ratio to multiply the weights used in the matching algorithm to control the delay that individual connections encounter. We demonstrate the improved characteristics of a switch using a ratio presenting results from simulations. The candidate also proposes a novel scheduling mechanism for an input queued ATM switch. In order to evaluate the performance of the scheduling mechanism in terms of throughput and fairness, the use of various metrics, initially proposed in the literature to evaluate output buffered switches are evaluated, adjusted and applied to input scheduling. In particular the Worst-case Fairness Index (WFl) which measures the maximum delay a connection will encounter is derived for use in input queued switches.
Description

Includes bibliographical references.

Keywords
Electrical Engineering

Reference:

Harvey, N. 2003. Design of a scheduling mechanism for an ATM switch. University of Cape Town.

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Masters