Characterizing Single Event Upsets within the lpGBT-based End-of-Substructure Card
| dc.contributor.advisor | Wyngaard, Janet | |
| dc.contributor.advisor | Keaveney, James | |
| dc.contributor.author | Naidoo, Joash Nicholas | |
| dc.date.accessioned | 2022-03-10T09:54:12Z | |
| dc.date.available | 2022-03-10T09:54:12Z | |
| dc.date.issued | 2021 | |
| dc.date.updated | 2022-03-08T09:49:57Z | |
| dc.description.abstract | The CERN ATLAS particle physics experiment is currently undergoing a significant system upgrade (ATLAS Phase II upgrade). As a result of the upgrade the experiment's Inner Tracker (ITk) and the front-end electronics of the ITk are being redesigned to handle increased data rates and a higher radiation environment. Within the ITk, the End Of Substructure (EoS) card is a new custom designed digital board that will provide the data, command, and power interface between on and off-detector electronics. Each EoS card makes use of one or two custom CERN designed low power Gigabit Transceivers (lpGBTs) ASICS that have been created for the purposes of supporting high bandwidth optical links in high radiation environments throughout CERN experiments. An estimated 1552 EoS cards will be installed in the ITk, each representing a potential point of failure. Given the complexity and quantity of new hardware designs involved, and that the EoS cards will be not be accessible or serviceable after the upgrade has been completed, there is a need for rigorous quality assurance (QA) and quality control (QC) testing. This thesis therefore describes an independent test setup commissioned, by the author, at the University of Cape Town (UCT) Physics Department for characterising aspects of EoS card's operation under representative radiation conditions. Specifically, the radiation environment of the ITk poses a challenge to electronics as energetic particles can deposit their energy within the circuit material resulting in an erroneous change in logic known as a Single Event Upset (SEU). The lpGBT is a radiation tolerant ASIC and employs digital signal processing (DSP) and triple modular redundancy (TMR) techniques to mitigate against the effects of SEUs on transmitted data. This thesis presents an experiment setup which tests this hypothesis that the DSP stages are susceptible to data corruption caused by SEUs. In addition the setup also attempts to characterize the susceptibility of the scrambler, encoder, and interleaver stages within the lpGBT to SEUs. This experiment is carried out by actively irradiating an EoS card with a neutron source (energy spectrum of up to 11 MeV), while emulating each stage on a non-irradiated off-board FPGA. Additionally and in support of this experiment, the existing firmware and LabView automation software developed at DESY are extended. Results from this thesis indicate that the DSP stages within the lpGBT are susceptible to data corruption caused by SEUs. It was also shown that the susceptibility of the experiment itself did not effect the measured SEU rates. Finally, preliminary results suggest that susceptibility of the DSP stages within the lpGBT can be characterized as the Bit Error Rate (BER) increases depending on the number of active stages. | |
| dc.identifier.apacitation | Naidoo, J. N. (2021). <i>Characterizing Single Event Upsets within the lpGBT-based End-of-Substructure Card</i>. (). ,Faculty of Engineering and the Built Environment ,Department of Electrical Engineering. Retrieved from http://hdl.handle.net/11427/36025 | en_ZA |
| dc.identifier.chicagocitation | Naidoo, Joash Nicholas. <i>"Characterizing Single Event Upsets within the lpGBT-based End-of-Substructure Card."</i> ., ,Faculty of Engineering and the Built Environment ,Department of Electrical Engineering, 2021. http://hdl.handle.net/11427/36025 | en_ZA |
| dc.identifier.citation | Naidoo, J.N. 2021. Characterizing Single Event Upsets within the lpGBT-based End-of-Substructure Card. . ,Faculty of Engineering and the Built Environment ,Department of Electrical Engineering. http://hdl.handle.net/11427/36025 | en_ZA |
| dc.identifier.ris | TY - Master Thesis AU - Naidoo, Joash Nicholas AB - The CERN ATLAS particle physics experiment is currently undergoing a significant system upgrade (ATLAS Phase II upgrade). As a result of the upgrade the experiment's Inner Tracker (ITk) and the front-end electronics of the ITk are being redesigned to handle increased data rates and a higher radiation environment. Within the ITk, the End Of Substructure (EoS) card is a new custom designed digital board that will provide the data, command, and power interface between on and off-detector electronics. Each EoS card makes use of one or two custom CERN designed low power Gigabit Transceivers (lpGBTs) ASICS that have been created for the purposes of supporting high bandwidth optical links in high radiation environments throughout CERN experiments. An estimated 1552 EoS cards will be installed in the ITk, each representing a potential point of failure. Given the complexity and quantity of new hardware designs involved, and that the EoS cards will be not be accessible or serviceable after the upgrade has been completed, there is a need for rigorous quality assurance (QA) and quality control (QC) testing. This thesis therefore describes an independent test setup commissioned, by the author, at the University of Cape Town (UCT) Physics Department for characterising aspects of EoS card's operation under representative radiation conditions. Specifically, the radiation environment of the ITk poses a challenge to electronics as energetic particles can deposit their energy within the circuit material resulting in an erroneous change in logic known as a Single Event Upset (SEU). The lpGBT is a radiation tolerant ASIC and employs digital signal processing (DSP) and triple modular redundancy (TMR) techniques to mitigate against the effects of SEUs on transmitted data. This thesis presents an experiment setup which tests this hypothesis that the DSP stages are susceptible to data corruption caused by SEUs. In addition the setup also attempts to characterize the susceptibility of the scrambler, encoder, and interleaver stages within the lpGBT to SEUs. This experiment is carried out by actively irradiating an EoS card with a neutron source (energy spectrum of up to 11 MeV), while emulating each stage on a non-irradiated off-board FPGA. Additionally and in support of this experiment, the existing firmware and LabView automation software developed at DESY are extended. Results from this thesis indicate that the DSP stages within the lpGBT are susceptible to data corruption caused by SEUs. It was also shown that the susceptibility of the experiment itself did not effect the measured SEU rates. Finally, preliminary results suggest that susceptibility of the DSP stages within the lpGBT can be characterized as the Bit Error Rate (BER) increases depending on the number of active stages. DA - 2021_ DB - OpenUCT DP - University of Cape Town KW - Electrical Engineering LK - https://open.uct.ac.za PY - 2021 T1 - Characterizing Single Event Upsets within the lpGBT-based End-of-Substructure Card TI - Characterizing Single Event Upsets within the lpGBT-based End-of-Substructure Card UR - http://hdl.handle.net/11427/36025 ER - | en_ZA |
| dc.identifier.uri | http://hdl.handle.net/11427/36025 | |
| dc.identifier.vancouvercitation | Naidoo JN. Characterizing Single Event Upsets within the lpGBT-based End-of-Substructure Card. []. ,Faculty of Engineering and the Built Environment ,Department of Electrical Engineering, 2021 [cited yyyy month dd]. Available from: http://hdl.handle.net/11427/36025 | en_ZA |
| dc.language.rfc3066 | eng | |
| dc.publisher.department | Department of Electrical Engineering | |
| dc.publisher.faculty | Faculty of Engineering and the Built Environment | |
| dc.subject | Electrical Engineering | |
| dc.title | Characterizing Single Event Upsets within the lpGBT-based End-of-Substructure Card | |
| dc.type | Master Thesis | |
| dc.type.qualificationlevel | Masters | |
| dc.type.qualificationlevel | MSc |