A reconfigurable accelerator card for high performance computing

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dc.contributor.advisorInggs, Michaelen_ZA
dc.contributor.advisorLangman, Alanen_ZA
dc.contributor.authorAitken, Michael Jamesen_ZA
dc.date.accessioned2014-07-31T10:59:54Z
dc.date.available2014-07-31T10:59:54Z
dc.date.issued2008en_ZA
dc.descriptionIncludes abstract.
dc.descriptionIncludes bibliographical references (leaves 68-70).
dc.description.abstractThis thesis describes the design, implementation, and testing of a reconfigurable accelerator card. The goal of the project was to provide a hardware platform for future students to carry out research into reconfigurable computing. Our accelerator design is an expansion card for a traditional Von Neumann host machine, and contains two field-programmable gate arrays. By inserting the card into a host machine, intrinsically parallel processing tasks can be exported to the FPGAs. This is similar to the way in which video game rendering tasks can be exported to the GFC on a graphics accelerator. We show how an FPGA is a suitable processing element, in terms of performance per watt, for many computing tasks. We set out to design and build a reconfigurable card that harnessed the latest FPGAs and fastest available I/O interfaces. The resultant design is one which can run within a host machine, in an array of host machines, or as a stand-alone processing node.en_ZA
dc.identifier.apacitationAitken, M. J. (2008). <i>A reconfigurable accelerator card for high performance computing</i>. (Thesis). University of Cape Town ,Faculty of Engineering & the Built Environment ,Department of Electrical Engineering. Retrieved from http://hdl.handle.net/11427/5234en_ZA
dc.identifier.chicagocitationAitken, Michael James. <i>"A reconfigurable accelerator card for high performance computing."</i> Thesis., University of Cape Town ,Faculty of Engineering & the Built Environment ,Department of Electrical Engineering, 2008. http://hdl.handle.net/11427/5234en_ZA
dc.identifier.citationAitken, M. 2008. A reconfigurable accelerator card for high performance computing. University of Cape Town.en_ZA
dc.identifier.ris TY - Thesis / Dissertation AU - Aitken, Michael James AB - This thesis describes the design, implementation, and testing of a reconfigurable accelerator card. The goal of the project was to provide a hardware platform for future students to carry out research into reconfigurable computing. Our accelerator design is an expansion card for a traditional Von Neumann host machine, and contains two field-programmable gate arrays. By inserting the card into a host machine, intrinsically parallel processing tasks can be exported to the FPGAs. This is similar to the way in which video game rendering tasks can be exported to the GFC on a graphics accelerator. We show how an FPGA is a suitable processing element, in terms of performance per watt, for many computing tasks. We set out to design and build a reconfigurable card that harnessed the latest FPGAs and fastest available I/O interfaces. The resultant design is one which can run within a host machine, in an array of host machines, or as a stand-alone processing node. DA - 2008 DB - OpenUCT DP - University of Cape Town LK - https://open.uct.ac.za PB - University of Cape Town PY - 2008 T1 - A reconfigurable accelerator card for high performance computing TI - A reconfigurable accelerator card for high performance computing UR - http://hdl.handle.net/11427/5234 ER - en_ZA
dc.identifier.urihttp://hdl.handle.net/11427/5234
dc.identifier.vancouvercitationAitken MJ. A reconfigurable accelerator card for high performance computing. [Thesis]. University of Cape Town ,Faculty of Engineering & the Built Environment ,Department of Electrical Engineering, 2008 [cited yyyy month dd]. Available from: http://hdl.handle.net/11427/5234en_ZA
dc.language.isoengen_ZA
dc.publisher.departmentDepartment of Electrical Engineeringen_ZA
dc.publisher.facultyFaculty of Engineering and the Built Environment
dc.publisher.institutionUniversity of Cape Town
dc.subject.otherElectrical Engineeringen_ZA
dc.titleA reconfigurable accelerator card for high performance computingen_ZA
dc.typeMaster Thesis
dc.type.qualificationlevelMasters
dc.type.qualificationnameMScen_ZA
uct.type.filetypeText
uct.type.filetypeImage
uct.type.publicationResearchen_ZA
uct.type.resourceThesisen_ZA
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