A domain specific language for facilitating automatic parallelization and placement of SDR patterns into heterogeneous computing architectures

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dc.contributor.advisorWinberg, Simonen_ZA
dc.contributor.advisorInggs, Michael Ren_ZA
dc.contributor.authorMohapi, Lerato Jerfreeen_ZA
dc.date.accessioned2018-01-22T12:41:48Z
dc.date.available2018-01-22T12:41:48Z
dc.date.issued2017en_ZA
dc.description.abstractThis thesis presents a domain-specific language (DSL) for software defined radio (SDR) which is referred to as OptiSDR. The main objective of OptiSDR is to facilitate the development and deployment of SDR applications into heterogeneous computing architectures (HCAs). As HCAs are becoming mainstream in SDR applications such as radar, radio astronomy, and telecommunications, parallel programming and optimization processes are also becoming cumbersome, complex, and time-consuming for SDR experts. Therefore, the OptiSDR DSL and its compiler framework were developed to alleviate these parallelization and optimization processes together with developing execution models for DSP and dataflow models of computation suitable for SDR-specific computations. The OptiSDR target HCAs are composed of graphics processing units (GPUs), multi-core central processing units (MCPUs), and field programmable gate arrays (FPGAs). The methodology used to implement the OptiSDR DSL involved an extensive review process of existing SDR tools and the extent to which they address the complexities associated with parallel programming and optimizing SDR applications for execution in HCAs. From this review process, it was discovered that, while HCAs are used to accelerate many SDR computations, there is a shortage of intuitive parallel programming frameworks that efficiently utilize the HCAs' computing resources for achieving adequate performance for SDR applications. There were, however, some very good general-purpose parallel programming frameworks identied in the literature review, including Python based tools such as NumbaPro and Copperhead, as well as the prevailing Delite embedded DSL compiler framework for heterogeneous targets. The Delite embedded DSL compiler framework motivated and powered the OptiSDR compiler development in that, it provides four main compiler development capabilities that are desired in OptiSDR: 1) Generic data parallel executable patterns; 2) Execution semantics for heterogeneous MCPU-GPU run-time; 3) Abstract syntax creation using intermediate representations (IR) nodes; and 4) Extensibility for defining new syntax for other domains. The OptiSDR DSL design processes using this Delite framework involved designing the new structured parallel patterns for DSP algorithms (e.g. FIR, FFT, convolution, correlation, etc.), dataflow models of computation (MoC), parallel loop optimizations (tiling and space splitting), and optimal memory access patterns. Advanced task and data parallel patterns were applied in the OptiSDR dataflow MoCs, which are especially suitable for SDR computations where FPGA-based realtime data acquisition systems feed data into multi-GPUs for implementation of parallel DSP algorithms. Furthermore, the research methodology involved an evaluation process that was used to determine the OptiSDR language's expressive power, efficiency, performance, accuracy, and ease of use in SDR applications, such as radar pulse compression and radio frequency sweeping algorithms. The results include measurements of performance and accuracy, productivity versus performance, and real-time processing speeds and accuracy. The performance of some of the regularly used modules, such as FFT-based Hilbert and cross-correlation was found to be very high, with computations speeds ranging from 70.0 GFLOPS to 72.6 GFLOPS, and speedups of up to 80× compared to sequential C/C++ programs and 50× for Matlab's parallel loops. Accuracy was favourable in most cases favourable. For instance, OptiSDR Octave-like DSP instantiations were found to be accurate, with L2 norm forward-errors ranging from 10⁻¹³ to 10⁻¹⁶for smaller and bigger SDR programs respectively. It can therefore be concluded from the analysis in this thesis that the objectives, which include alleviating the complexities in parallel programming and optimizing SDR applications for execution in HCAs, were met. Moreover, the following hypothesis was validated, namely: "It is possible to design a DSL to facilitate the development of SDR applications and their deployment on HCAs without significant degradation of software performance, and with possible improvement in the automatically emitted low-level source code quality.". It was validated by; 1) Defining the OptiSDR attributes such as parallel DSP patterns and dataflow MoCs; 2) Providing parameterizable SDR modules with automatic parallelization and optimization for performance and accuracy; and 3) Presenting a set of intuitive validation constructs for accuracy testing using root-mean square error, and functional verification of DSP using two-dimensional graphics plotting for radar and real-time spectral analysis plots.en_ZA
dc.identifier.apacitationMohapi, L. J. (2017). <i>A domain specific language for facilitating automatic parallelization and placement of SDR patterns into heterogeneous computing architectures</i>. (Thesis). University of Cape Town ,Faculty of Engineering & the Built Environment ,Department of Electrical Engineering. Retrieved from http://hdl.handle.net/11427/26860en_ZA
dc.identifier.chicagocitationMohapi, Lerato Jerfree. <i>"A domain specific language for facilitating automatic parallelization and placement of SDR patterns into heterogeneous computing architectures."</i> Thesis., University of Cape Town ,Faculty of Engineering & the Built Environment ,Department of Electrical Engineering, 2017. http://hdl.handle.net/11427/26860en_ZA
dc.identifier.citationMohapi, L. 2017. A domain specific language for facilitating automatic parallelization and placement of SDR patterns into heterogeneous computing architectures. University of Cape Town.en_ZA
dc.identifier.ris TY - Thesis / Dissertation AU - Mohapi, Lerato Jerfree AB - This thesis presents a domain-specific language (DSL) for software defined radio (SDR) which is referred to as OptiSDR. The main objective of OptiSDR is to facilitate the development and deployment of SDR applications into heterogeneous computing architectures (HCAs). As HCAs are becoming mainstream in SDR applications such as radar, radio astronomy, and telecommunications, parallel programming and optimization processes are also becoming cumbersome, complex, and time-consuming for SDR experts. Therefore, the OptiSDR DSL and its compiler framework were developed to alleviate these parallelization and optimization processes together with developing execution models for DSP and dataflow models of computation suitable for SDR-specific computations. The OptiSDR target HCAs are composed of graphics processing units (GPUs), multi-core central processing units (MCPUs), and field programmable gate arrays (FPGAs). The methodology used to implement the OptiSDR DSL involved an extensive review process of existing SDR tools and the extent to which they address the complexities associated with parallel programming and optimizing SDR applications for execution in HCAs. From this review process, it was discovered that, while HCAs are used to accelerate many SDR computations, there is a shortage of intuitive parallel programming frameworks that efficiently utilize the HCAs' computing resources for achieving adequate performance for SDR applications. There were, however, some very good general-purpose parallel programming frameworks identied in the literature review, including Python based tools such as NumbaPro and Copperhead, as well as the prevailing Delite embedded DSL compiler framework for heterogeneous targets. The Delite embedded DSL compiler framework motivated and powered the OptiSDR compiler development in that, it provides four main compiler development capabilities that are desired in OptiSDR: 1) Generic data parallel executable patterns; 2) Execution semantics for heterogeneous MCPU-GPU run-time; 3) Abstract syntax creation using intermediate representations (IR) nodes; and 4) Extensibility for defining new syntax for other domains. The OptiSDR DSL design processes using this Delite framework involved designing the new structured parallel patterns for DSP algorithms (e.g. FIR, FFT, convolution, correlation, etc.), dataflow models of computation (MoC), parallel loop optimizations (tiling and space splitting), and optimal memory access patterns. Advanced task and data parallel patterns were applied in the OptiSDR dataflow MoCs, which are especially suitable for SDR computations where FPGA-based realtime data acquisition systems feed data into multi-GPUs for implementation of parallel DSP algorithms. Furthermore, the research methodology involved an evaluation process that was used to determine the OptiSDR language's expressive power, efficiency, performance, accuracy, and ease of use in SDR applications, such as radar pulse compression and radio frequency sweeping algorithms. The results include measurements of performance and accuracy, productivity versus performance, and real-time processing speeds and accuracy. The performance of some of the regularly used modules, such as FFT-based Hilbert and cross-correlation was found to be very high, with computations speeds ranging from 70.0 GFLOPS to 72.6 GFLOPS, and speedups of up to 80× compared to sequential C/C++ programs and 50× for Matlab's parallel loops. Accuracy was favourable in most cases favourable. For instance, OptiSDR Octave-like DSP instantiations were found to be accurate, with L2 norm forward-errors ranging from 10⁻¹³ to 10⁻¹⁶for smaller and bigger SDR programs respectively. It can therefore be concluded from the analysis in this thesis that the objectives, which include alleviating the complexities in parallel programming and optimizing SDR applications for execution in HCAs, were met. Moreover, the following hypothesis was validated, namely: "It is possible to design a DSL to facilitate the development of SDR applications and their deployment on HCAs without significant degradation of software performance, and with possible improvement in the automatically emitted low-level source code quality.". It was validated by; 1) Defining the OptiSDR attributes such as parallel DSP patterns and dataflow MoCs; 2) Providing parameterizable SDR modules with automatic parallelization and optimization for performance and accuracy; and 3) Presenting a set of intuitive validation constructs for accuracy testing using root-mean square error, and functional verification of DSP using two-dimensional graphics plotting for radar and real-time spectral analysis plots. DA - 2017 DB - OpenUCT DP - University of Cape Town LK - https://open.uct.ac.za PB - University of Cape Town PY - 2017 T1 - A domain specific language for facilitating automatic parallelization and placement of SDR patterns into heterogeneous computing architectures TI - A domain specific language for facilitating automatic parallelization and placement of SDR patterns into heterogeneous computing architectures UR - http://hdl.handle.net/11427/26860 ER - en_ZA
dc.identifier.urihttp://hdl.handle.net/11427/26860
dc.identifier.vancouvercitationMohapi LJ. A domain specific language for facilitating automatic parallelization and placement of SDR patterns into heterogeneous computing architectures. [Thesis]. University of Cape Town ,Faculty of Engineering & the Built Environment ,Department of Electrical Engineering, 2017 [cited yyyy month dd]. Available from: http://hdl.handle.net/11427/26860en_ZA
dc.language.isoengen_ZA
dc.publisher.departmentDepartment of Electrical Engineeringen_ZA
dc.publisher.facultyFaculty of Engineering and the Built Environment
dc.publisher.institutionUniversity of Cape Town
dc.subject.otherElectrical Engineeringen_ZA
dc.titleA domain specific language for facilitating automatic parallelization and placement of SDR patterns into heterogeneous computing architecturesen_ZA
dc.typeDoctoral Thesis
dc.type.qualificationlevelDoctoral
dc.type.qualificationnamePhDen_ZA
uct.type.filetypeText
uct.type.filetypeImage
uct.type.publicationResearchen_ZA
uct.type.resourceThesisen_ZA
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