Implementation of a low cost demonstrator riometer on a flexible FPGA backend: The first steps in adding a riometer mode to the digital SuperDARN radar at SANAE IV

Master Thesis


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University of Cape Town

SuperDARN is an international network of 35 HF radars located near the poles of the Earth dedicated to determining the state of the ionosphere at high latitudes. One of the SuperDARN radars is located at South Africa's base in Antarctica (SANAE IV) and is administered by the South African National Space Association (SANSA). The radar at SANAE IV was recently upgraded to a fully digital transceiver, with the addition of a Field Programmable Gate Array (FPGA) at the core of this upgrade. FPGAs allow for easy hardware reconfiguration and high-performance computing. The aim of this project is to determine the feasibility of using the FPGA on board the radar at SANAE IV to implement a riometer mode to run simultaneously with its main mode of operation, adding a new tool to the radar's set of abilities without any investment in new hardware. The riometer function could easily be ported to other radars in the SuperDARN network, allowing for a significant increase in riometer coverage of the polar regions. As a first step towards achieving this goal, a demonstrator riometer is developed using the Red Pitaya FPGA platform as its backend, and tested at the University of Cape Town, at SANSA in Hermanus and at Fish Hoek. A riometer measures the opacity of the ionosphere with respect to cosmic radiation. Doing this over a wide band of frequencies results in a spectral riometer. This dissertation describes the design and implementation of both a single frequency and a spectral riometer, both implemented on the Red Pitaya, and the results of testing these implementations. Experimentation alongside a La Jolla 38MHz riometer revealed very similar performance for the low-cost demonstrator riometer. It is thereby shown that low cost HF riometry is possible and that it is feasible to implement a riometer on the radar at SANAE IV. However, an additional FPGA is required.