Supply-friendly single phase uninteruptible power supply

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dc.contributor.advisorMalengret, Michelen_ZA
dc.contributor.authorMills, Carlo Juanen_ZA
dc.date.accessioned2016-01-02T04:19:40Z
dc.date.available2016-01-02T04:19:40Z
dc.date.issued1998en_ZA
dc.descriptionIncludes bibliography.en_ZA
dc.description.abstractUninterruptible power supplies (UPS) maintain a constant supply of power to a critical load. The distinguishing features are a fixed voltage and frequency, low harmonic content and the ability to supply the load for a period of time after the incoming supply has failed. The document begins by identifying the typical power-line disturbances and their effect on various types of equipment. Together with the power conditioners used to suppress these disturbances, various UPS standby, line-interactive and on-line configurations are introduced. Next, the possibility of modifying a locally manufactured UPS to meet the design specifications is investigated. The performance of the system under load is evaluated, and forms the basis for the following decision. Due to the large number of modifications required and the inflexibility of local UPS topology, an alternative topology is adopted. In the new topology a power factor corrector, constructed around a DC to DC boost converter, interfaces with the incoming AC line. It delivers a half sinusoidal current into the DC bus. An IGBT inverter using sinusoidal unipolar pulse-width modulation regenerates the AC load voltage after filtering through a LC-filter. The DC bus voltage ripple is reduced by synchronising the inverter load and power factor corrector current while the battery pack maintains the DC bus during a power failure. The power factor corrector employs a dedicated analogue controller chip while a MCS-51 microcontroller generates the inverter PWM, provides the remote monitoring facilities, battery charging and performs general support tasks. The total harmonic distortion of the input current is measured at less than 4% while the power factor remained above 0.99 over the entire load range. The ripple regulator reduced the DC bus voltage ripple without any noticeable effect on the load. Under maximum load, the steady state output voltage is maintained during the -20%, +10% variation in the incoming line voltage. However, the transient response fails to meet the 5% design specification. A 0-100% load step results in a 7% drop in the output voltage while the loss of the load results 10% jump in voltage. System efficiency is measured at 85%. It is the lack of processing power, precluding the use of floating point or an optimal control algorithm, which ultimately compromises the performance of the system. It is recommended that the microcontroller be replaced with a 16-bit processor or digital signal processor to provide the extra computational power needed to optimise the UPS response. To improve the voltage regulation, it is recommended that the control include an inner current loop while the switching frequency should be increased to reduce the energy storage in the output filter. Further adjustments and refinements to the topology are suggested in the final chapter.en_ZA
dc.identifier.apacitationMills, C. J. (1998). <i>Supply-friendly single phase uninteruptible power supply</i>. (Thesis). University of Cape Town ,Faculty of Engineering & the Built Environment ,Department of Electrical Engineering. Retrieved from http://hdl.handle.net/11427/16095en_ZA
dc.identifier.chicagocitationMills, Carlo Juan. <i>"Supply-friendly single phase uninteruptible power supply."</i> Thesis., University of Cape Town ,Faculty of Engineering & the Built Environment ,Department of Electrical Engineering, 1998. http://hdl.handle.net/11427/16095en_ZA
dc.identifier.citationMills, C. 1998. Supply-friendly single phase uninteruptible power supply. University of Cape Town.en_ZA
dc.identifier.ris TY - Thesis / Dissertation AU - Mills, Carlo Juan AB - Uninterruptible power supplies (UPS) maintain a constant supply of power to a critical load. The distinguishing features are a fixed voltage and frequency, low harmonic content and the ability to supply the load for a period of time after the incoming supply has failed. The document begins by identifying the typical power-line disturbances and their effect on various types of equipment. Together with the power conditioners used to suppress these disturbances, various UPS standby, line-interactive and on-line configurations are introduced. Next, the possibility of modifying a locally manufactured UPS to meet the design specifications is investigated. The performance of the system under load is evaluated, and forms the basis for the following decision. Due to the large number of modifications required and the inflexibility of local UPS topology, an alternative topology is adopted. In the new topology a power factor corrector, constructed around a DC to DC boost converter, interfaces with the incoming AC line. It delivers a half sinusoidal current into the DC bus. An IGBT inverter using sinusoidal unipolar pulse-width modulation regenerates the AC load voltage after filtering through a LC-filter. The DC bus voltage ripple is reduced by synchronising the inverter load and power factor corrector current while the battery pack maintains the DC bus during a power failure. The power factor corrector employs a dedicated analogue controller chip while a MCS-51 microcontroller generates the inverter PWM, provides the remote monitoring facilities, battery charging and performs general support tasks. The total harmonic distortion of the input current is measured at less than 4% while the power factor remained above 0.99 over the entire load range. The ripple regulator reduced the DC bus voltage ripple without any noticeable effect on the load. Under maximum load, the steady state output voltage is maintained during the -20%, +10% variation in the incoming line voltage. However, the transient response fails to meet the 5% design specification. A 0-100% load step results in a 7% drop in the output voltage while the loss of the load results 10% jump in voltage. System efficiency is measured at 85%. It is the lack of processing power, precluding the use of floating point or an optimal control algorithm, which ultimately compromises the performance of the system. It is recommended that the microcontroller be replaced with a 16-bit processor or digital signal processor to provide the extra computational power needed to optimise the UPS response. To improve the voltage regulation, it is recommended that the control include an inner current loop while the switching frequency should be increased to reduce the energy storage in the output filter. Further adjustments and refinements to the topology are suggested in the final chapter. DA - 1998 DB - OpenUCT DP - University of Cape Town LK - https://open.uct.ac.za PB - University of Cape Town PY - 1998 T1 - Supply-friendly single phase uninteruptible power supply TI - Supply-friendly single phase uninteruptible power supply UR - http://hdl.handle.net/11427/16095 ER - en_ZA
dc.identifier.urihttp://hdl.handle.net/11427/16095
dc.identifier.vancouvercitationMills CJ. Supply-friendly single phase uninteruptible power supply. [Thesis]. University of Cape Town ,Faculty of Engineering & the Built Environment ,Department of Electrical Engineering, 1998 [cited yyyy month dd]. Available from: http://hdl.handle.net/11427/16095en_ZA
dc.language.isoengen_ZA
dc.publisher.departmentDepartment of Electrical Engineeringen_ZA
dc.publisher.facultyFaculty of Engineering and the Built Environment
dc.publisher.institutionUniversity of Cape Town
dc.subject.otherElectrical and Electronic Engineeringen_ZA
dc.titleSupply-friendly single phase uninteruptible power supplyen_ZA
dc.typeMaster Thesis
dc.type.qualificationlevelMasters
dc.type.qualificationnameMScen_ZA
uct.type.filetypeText
uct.type.filetypeImage
uct.type.publicationResearchen_ZA
uct.type.resourceThesisen_ZA
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