The development of a node for a hardware reconfigurable parallel processor

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dc.contributor.advisorInggs, Michaelen_ZA
dc.contributor.authorVan Schaik, Carl Fransen_ZA
dc.date.accessioned2016-03-30T14:44:52Z
dc.date.available2016-03-30T14:44:52Z
dc.date.issued2002en_ZA
dc.description.abstractThis dissertation concerns the design and implementation of a node for a hardware reconfigurable parallel processor. The hardware that was developed allows for the further development of a parallel processor with configurable hardware acceleration. Each node in the system has a standard microprocessor and reconfigurable logic device and has high speed communications channels for inter-node communication. The design of the node provided high-speed serial communications channels allowing the implementation of various network topographies. The node also provided a PCI master interface to provide an external interface and communicate with local nodes on the bus. A high speed RlSC processor provided communication and system control functions and the reconfigurable logic device provided communication interfaces and data processing functions. The node was designed and implemented as a PCI card that interfaced a standard PCI bus. VHDL designs for logic devices that provided system support were developed, VHDL designs for the reconfigurable logic FPGA and software including drivers and system software were written for the node. The 64-bit version Linux operating system was then ported to the processor providing a UNIX environment for the system. The node functioned as specified and parallel and hardware accelerated processing was demonstrated. The hardware acceleration was shown to provide substantial performance benefits for the system.en_ZA
dc.identifier.apacitationVan Schaik, C. F. (2002). <i>The development of a node for a hardware reconfigurable parallel processor</i>. (Thesis). University of Cape Town ,Faculty of Engineering & the Built Environment ,Department of Electrical Engineering. Retrieved from http://hdl.handle.net/11427/18411en_ZA
dc.identifier.chicagocitationVan Schaik, Carl Frans. <i>"The development of a node for a hardware reconfigurable parallel processor."</i> Thesis., University of Cape Town ,Faculty of Engineering & the Built Environment ,Department of Electrical Engineering, 2002. http://hdl.handle.net/11427/18411en_ZA
dc.identifier.citationVan Schaik, C. 2002. The development of a node for a hardware reconfigurable parallel processor. University of Cape Town.en_ZA
dc.identifier.ris TY - Thesis / Dissertation AU - Van Schaik, Carl Frans AB - This dissertation concerns the design and implementation of a node for a hardware reconfigurable parallel processor. The hardware that was developed allows for the further development of a parallel processor with configurable hardware acceleration. Each node in the system has a standard microprocessor and reconfigurable logic device and has high speed communications channels for inter-node communication. The design of the node provided high-speed serial communications channels allowing the implementation of various network topographies. The node also provided a PCI master interface to provide an external interface and communicate with local nodes on the bus. A high speed RlSC processor provided communication and system control functions and the reconfigurable logic device provided communication interfaces and data processing functions. The node was designed and implemented as a PCI card that interfaced a standard PCI bus. VHDL designs for logic devices that provided system support were developed, VHDL designs for the reconfigurable logic FPGA and software including drivers and system software were written for the node. The 64-bit version Linux operating system was then ported to the processor providing a UNIX environment for the system. The node functioned as specified and parallel and hardware accelerated processing was demonstrated. The hardware acceleration was shown to provide substantial performance benefits for the system. DA - 2002 DB - OpenUCT DP - University of Cape Town LK - https://open.uct.ac.za PB - University of Cape Town PY - 2002 T1 - The development of a node for a hardware reconfigurable parallel processor TI - The development of a node for a hardware reconfigurable parallel processor UR - http://hdl.handle.net/11427/18411 ER - en_ZA
dc.identifier.urihttp://hdl.handle.net/11427/18411
dc.identifier.vancouvercitationVan Schaik CF. The development of a node for a hardware reconfigurable parallel processor. [Thesis]. University of Cape Town ,Faculty of Engineering & the Built Environment ,Department of Electrical Engineering, 2002 [cited yyyy month dd]. Available from: http://hdl.handle.net/11427/18411en_ZA
dc.language.isoengen_ZA
dc.publisher.departmentDepartment of Electrical Engineeringen_ZA
dc.publisher.facultyFaculty of Engineering and the Built Environment
dc.publisher.institutionUniversity of Cape Town
dc.subject.otherElectrical Engineeringen_ZA
dc.titleThe development of a node for a hardware reconfigurable parallel processoren_ZA
dc.typeMaster Thesis
dc.type.qualificationlevelMasters
dc.type.qualificationnameMScen_ZA
uct.type.filetypeText
uct.type.filetypeImage
uct.type.publicationResearchen_ZA
uct.type.resourceThesisen_ZA
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